PCB Stack-up Builder

Engineering Tools — Impedance Preview
Impedance Preview
Layer Stack
4
Copper Layers
1.57
Total (mm)
2
Signal Layers
2
Plane Layers
Cross-Section & Impedance
Trace Parameters for Impedance
Calculated Impedance
Stack-up Notes
Standard 4-layer stack-up. Suitable for mixed-signal designs up to 1 GHz.

PCB Stack-up Design Guide

A well-designed PCB stack-up is crucial for signal integrity, EMI control, and manufacturability. The arrangement of signal and plane layers, along with dielectric materials, determines impedance, crosstalk, and power delivery performance.

Microstrip: Z₀ ≈ (87 / √(εᵣ + 1.41)) × ln(5.98h / (0.8w + t))

Stripline: Z₀ ≈ (60 / √εᵣ) × ln(4h / (0.67π × (0.8w + t)))

Where εᵣ is dielectric constant, h is height to reference plane, w is trace width, and t is copper thickness. Accurate within ~5% for typical PCB geometries.

Common Dielectric Materials
  • FR4 Standard — εᵣ = 4.2–4.5, low cost
  • High-Speed FR4 — εᵣ = 3.8–4.0, better Df
  • Rogers 4350B — εᵣ = 3.48, RF/microwave
  • Megtron 6 — εᵣ = 3.4, high-speed digital
Layer Pairing Rules
  • Signal layers should reference solid planes
  • Keep high-speed signals adjacent to GND
  • Avoid routing over plane splits
  • Balance copper symmetrically to prevent warpage
Impedance Targets
  • 50Ω — Single-ended (USB, SPI, general)
  • 90Ω — Differential (USB 2.0/3.0)
  • 100Ω — Differential (Ethernet, LVDS)
  • 85Ω — Differential (HDMI, DisplayPort)
Manufacturing Tolerances
  • Impedance: ±10% standard, ±5% tight
  • Dielectric thickness: ±10%
  • Trace width: ±0.5–1.0 mil
  • Registration: ±2–3 mils layer-to-layer

Design Tip: For controlled impedance, always consult your fabricator's capabilities and request their recommended stack-up. Actual impedance depends on their specific materials and processes. This calculator provides estimates for early design planning.