Electrical Test — commonly known as E-Test — is the last line of defense before a bare PCB leaves the fabrication facility. No matter how well a board is designed, bypassing or underestimating this verification step is a reliable way to ship expensive scrap. This guide covers everything you need to know about PCB E-Test: the core principles, available testing methods, relevant industry standards, and practical design tips that make testing faster and more effective.

Whether you are ordering a handful of prototype boards or ramping up to full production, a solid understanding of E-Test will sharpen your conversations with PCB suppliers, reduce defect escapes, and protect your project budget.

What Is PCB E-Test?

E-Test, short for Electrical Test, is a verification procedure applied to bare (unpopulated) printed circuit boards. Its purpose is to confirm that every electrical connection on the board matches the original design intent. The process focuses on two fundamental checks:

Continuity Testing (Opens Detection)

This check confirms that every node belonging to the same net is properly connected. An open occurs when a trace, via, or junction that should carry current is broken or absent — preventing the circuit from functioning as designed.

Isolation Testing (Shorts Detection)

This check verifies that nets which are supposed to remain electrically separate are not accidentally bridged. A short can result from copper residue between traces, solder mask registration errors, or etching defects that leave unintended conductive paths.

E-Test is governed by the IPC-9252 standard, which defines the requirements and procedures for electrically testing unpopulated printed boards. Test equipment applies controlled voltage signals through probes and evaluates the resulting resistance measurements to determine pass or fail status at each test point.

Why E-Test Has Become Indispensable

In earlier generations of PCB design, visual inspection was often sufficient to catch most manufacturing defects. Traces were wide, layer counts were low, and a trained eye could spot problems under magnification. That era is over. Contemporary boards routinely feature:

• Blind and buried vias that are entirely hidden from the board surface
• HDI trace geometries with widths as narrow as 0.075 mm (3 mil)
• Stackups exceeding 20 layers with intricate internal interconnections
• BGA escape routing that is physically inaccessible to optical inspection

Consider a buried via on layer 4 that is supposed to connect to layer 8. No optical system can verify that connection from the outside. AOI captures the surface; E-Test captures electrical reality. These two inspection methods address entirely different failure modes and are not interchangeable.

E-Test Methods: Flying Probe vs. Fixture Testing

Two primary methods are used to perform E-Test. Selecting the right one comes down to your production volume, budget constraints, and how frequently the design is likely to change.

Flying Probe Testing

Flying probe systems use motorized probe heads — typically between four and eight — that traverse the PCB surface under software control. A test program is generated from your netlist data, directing each probe to contact designated test points in sequence. The probes move independently, allowing coverage of virtually any board layout without custom tooling.

How It Works

• The board is loaded and secured on the test platform
• Probe heads navigate to each target location: pads, vias, and component footprints
• Continuity and isolation measurements are performed sequentially at each point
• Results are logged and compared against the netlist to flag any discrepancies

 

Best Suited For

• Engineering prototypes and pre-production samples
• Low-to-medium volume runs, generally under 500 boards
• Designs that undergo frequent revisions
• Complex HDI layouts with limited probe access

 

Fixture Testing (Bed of Nails)

Fixture testing relies on a custom-built test fixture populated with spring-loaded pogo pins, each precisely positioned to align with a specific test point on your PCB. When the board is pressed onto the fixture, every test point makes contact simultaneously, enabling parallel measurement across the entire board in a matter of seconds.

How It Works

• A dedicated fixture is engineered and fabricated for your specific board layout
• The board is placed onto the fixture and clamped into contact
• All test points are probed in parallel in a single pass
• Full electrical verification is completed in seconds

 

Best Suited For

• High-volume production runs, typically 1,000 boards or more
• Mature designs with minimal anticipated revisions
• Applications where throughput speed is a priority

 

Side-by-Side Comparison

Factor	Flying Probe	Fixture (Bed of Nails)
Fixture Cost	None — no tooling required	$500 to $20,000+ depending on complexity
Setup Time	Hours (automated program generation)	Days to weeks (engineering and fabrication)
Test Time per Board	1 to 5 minutes	5 to 30 seconds
Design Flexibility	High — program updates are straightforward	Low — design changes require a new fixture
Minimum Pitch	0.1 mm (4 mil)	0.5 mm (20 mil) for standard fixtures
Recommended Volume	1 to 500 units	500 units and above
Per-Board Cost at Scale	Higher as volume increases	Lower as volume increases

Practical note: many manufacturers offer a hybrid approach — flying probe for qualification and early production, transitioning to fixture testing once the design is stable and volumes justify the tooling investment.

The IPC-D-356 Netlist Format

Before any probing can take place, the test system needs a complete and accurate description of your board’s electrical connectivity. The IPC-D-356 format (also referred to as IPC-356) is the industry-standard netlist file specifically designed for electrical testing purposes, and it is accepted by virtually every PCB manufacturer worldwide.

Contents of an IPC-D-356 File

IPC-D-356 is a plain ASCII text file that encodes the following information:

• Net names: unique identifiers for each electrical network on the board
• Test point coordinates: X/Y locations where probes will make contact
• Pin assignments: mapping of component reference designators to their respective nets
• Layer access data: which board layers are accessible for probing at each point
• Via and hole data: locations of through-holes and vias throughout the stackup

 

Why Providing Your Own Netlist Matters

Exporting an IPC-D-356 file directly from your CAD tool and including it with your fabrication package offers several concrete advantages:

• Your manufacturer can cross-check the Gerber files for consistency before production begins
• CAM processing errors can be caught and corrected at the data review stage
• Test coverage can be verified against your actual design intent rather than inferred data

 

Without a supplied netlist, your manufacturer will extract connectivity information from the Gerber files themselves. This approach works, but it is only as reliable as the Gerber output — if your files contain errors, those errors will carry into the test program.

Exporting IPC-D-356 from Common CAD Tools

 

CAD Tool	Export Path
Altium Designer	File > Fabrication Outputs > Test Point Report > Enable IPC-D-356A
KiCad	File > Fabrication Outputs > IPC-D-356 Netlist File
OrCAD / Allegro	Manufacture > NC > IPC-356
PADS	File > CAM > IPC-D-356

 

IPC-9252 Testing Standards and Classification

IPC-9252 defines testing requirements at different levels based on the intended end-use of the board. Specifying the correct class in your documentation ensures that your manufacturer applies the appropriate test parameters.

IPC Testing Class Summary

Class	Target Application	Continuity Threshold	Isolation Voltage	Typical Use Cases
Class 1	General Electronics	50 ohm or less	40 VDC or greater	Consumer goods, toys
Class 2	Dedicated Service	20 ohm or less	100 VDC or greater	Industrial, telecom equipment
Class 3	High Reliability	10 ohm or less	250 VDC or greater	Medical devices, defense, aerospace
Class 3/A	Aerospace / Military Avionics	10 ohm or less	250 VDC or greater, 100 Mohm insulation	Flight-critical systems

Higher isolation voltages expose marginal shorts and surface contamination that lower voltages may fail to detect. For safety-critical applications, explicitly specifying the required test class is not optional — it directly affects the rigor of the test being applied.

What Gets Measured During E-Test

Test Type	What It Evaluates	Pass Criterion
Opens Test	Current flow between nodes within the same net	Resistance below the defined threshold (e.g., under 10 ohm)
Shorts Test	Electrical isolation between separate nets	Resistance above the defined threshold (e.g., over 20 Mohm)
100% Netlist Test	Every node on every net in the design	Complete coverage with no exceptions
Optimized Netlist Test	Net endpoints plus selected intermediate points	Faster execution, slightly reduced coverage
Hi-Pot Test	High-voltage insulation integrity	No dielectric breakdown at the specified voltage
4-Wire Kelvin Test	Precise low-resistance measurement	Milliohm-level accuracy, unaffected by lead resistance

 

The E-Test Workflow: Inside the Factory

Understanding how E-Test is executed helps clarify why complete and accurate documentation matters, and gives you a realistic picture of the timeline at each stage.

Step 1: Test Program Generation

Before any board is probed, the test system must be programmed. The manufacturer’s CAM engineering team will:

• Import your netlist (IPC-D-356 file or Gerber-extracted equivalent)
• Identify all accessible test points, including pads, vias, and component footprints
• Plan an optimized probe path for flying probe efficiency
• Configure test parameters to match your specified IPC class requirements
• Validate the resulting program against your design data

 

For flying probe, this step is largely automated and typically takes one to four hours. Fixture design involves hands-on engineering work and commonly requires two to five business days.

Step 2: First Article Inspection

The initial boards coming off the production line receive heightened scrutiny:

• Full 100% netlist verification is performed
• Any failures trigger detailed fault isolation and root cause investigation
• Results are compared against the original design intent
• Documentation is generated to support traceability requirements

 

First article results should be reviewed and approved before authorizing the full production run.

Step 3: Production Testing

During the production run, every board passes through E-Test:

• Flying probe: boards are tested individually with full netlist coverage
• Fixture: panel fixtures can enable simultaneous testing of multiple boards
• Real-time logging: test data is recorded automatically for quality tracking
• Automatic rejection: failing boards are flagged and physically separated

 

Step 4: Failure Analysis and Reporting

When boards fail, the test system captures detailed diagnostic information:

• Net names associated with each open or short condition
• Physical coordinates of each fault location on the board
• Resistance measurements recorded at each failure point
• Visual maps highlighting defect locations across the panel

 

A capable manufacturer will share this data with you proactively, particularly during first article review or when investigating yield problems.

Defects That E-Test Catches

E-Test intercepts manufacturing defects that would otherwise cause functional failures in the field. Here is a breakdown of what the process typically uncovers.

Root Causes of Open Circuit Failures

• Incomplete trace etching leaving gaps in conductive paths
• Drill registration errors where the via bore misses its target pad
• Broken internal traces in multilayer boards caused by lamination stress
• Contamination preventing adequate copper adhesion during plating
• Cracked annular rings from mechanical stress or thermal cycling

 

Root Causes of Short Circuit Failures

• Copper residue bridging adjacent traces due to insufficient etching
• Solder mask registration errors exposing conductors that should be covered
• Fine-pitch bridging in areas with tight trace spacing
• Inner layer misalignment creating unintended copper overlap
• CAM errors introduced during panelization processing

 

A Real-World Example

On a 12-layer HDI board, every panel passed both visual inspection and AOI without a single flag. E-Test subsequently identified that approximately 3% of boards had open circuits in buried vias between layers 5 and 6 — a defect that is completely invisible from the board surface. Without E-Test, those boards would have proceeded to component assembly, consuming expensive parts and adding weeks to the project schedule before the problem surfaced.

Design for Testability (DFT) Best Practices

Design decisions made during layout directly affect how thorough and cost-effective E-Test can be. The following recommendations improve test coverage and reduce the risk of probe access problems.

Test Point Placement Guidelines

• Add dedicated test pads on critical nets wherever board space allows
• Keep test points clear of component bodies that would obstruct probe access
• Maintain at least 0.5 mm spacing between adjacent test points for fixture compatibility
• Arrange test points on a regular grid if fixture testing is anticipated
• For via-in-pad designs, verify that another accessible test location exists elsewhere on the same net

 

Netlist Hygiene

• Clean up anonymous or unnamed nets before exporting — remove any that are not intentional
• Flag intentional shorts (such as fused jumpers or zero-ohm links) so they are not classified as failures
• Include power and ground planes in the netlist to ensure comprehensive test coverage

 

When to Require 100% E-Test

Make 100% electrical test a mandatory requirement for:

• All first article inspections (FAI)
• Medical, aerospace, automotive, and other high-reliability applications
• Boards with eight or more layers
• Any design incorporating blind or buried vias
• Production qualification runs

 

Frequently Asked Questions

What is the difference between E-Test and ICT?

E-Test is performed on bare boards before component assembly. It verifies the integrity of the copper network — checking for opens and shorts in the PCB itself. ICT (In-Circuit Test) is performed after assembly and evaluates component values, orientation, and circuit functionality. E-Test catches fabrication defects; ICT catches assembly defects. The two serve different purposes and neither replaces the other.

How much does E-Test cost?

Most PCB manufacturers bundle basic E-Test into their standard fabrication pricing. Flying probe is typically included at no extra charge for small quantities. Fixture-based testing carries a one-time tooling cost — ranging from several hundred to tens of thousands of dollars depending on board complexity — offset by lower per-board costs at volume. Always confirm the scope of testing included in your quote.

Can E-Test find all PCB defects?

No. E-Test is limited to electrical connectivity. It cannot detect:

• Dimensional non-conformances such as incorrect trace width or hole diameter
• Solder mask voids or inclusions that do not create electrical shorts
• Surface contamination that falls below the isolation threshold
• Mechanical issues including warpage, delamination, or drill breakout

 

For comprehensive quality assurance, combine E-Test with AOI and dimensional inspection.

Is E-Test necessary for prototype boards?

Yes, without question. Prototype builds are precisely where undetected fabrication defects cause the most damage — they consume debugging time and delay the design iteration cycle. Knowing that your bare boards are electrically correct before populating them eliminates one variable from the equation. If the assembled prototype fails, you know the cause lies in the design or assembly, not the board itself.

What does 100% E-Test actually mean?

It means every board in your order is electrically tested — not a sample, not a subset. Every net is checked for continuity, and isolation is verified between all net pairs. This is the standard practice at reputable manufacturers and should be treated as the baseline expectation, not a premium option.

Troubleshooting E-Test Failures

A failing E-Test report is not a crisis — most failures fall into recognizable patterns with clear investigative paths.

Diagnosing Open Circuit Failures

Observed Symptom	Probable Cause	Recommended Action
Opens on multiple vias	Drill registration error	Review drill-to-copper alignment tolerances
Opens on fine-pitch traces	Over-etching or under-etching	Audit etching process parameters
Opens on inner layers	Lamination void or contamination	Request cross-section microsection analysis
Random opens across the board	Plating adhesion failure	Investigate surface preparation process

 

Diagnosing Short Circuit Failures

Observed Symptom	Probable Cause	Recommended Action
Shorts between adjacent traces	Insufficient etching	Reduce trace density or tighten etch control
Shorts on power or ground planes	Inner layer misregistration	Review layer-to-layer alignment tolerances
Random shorts across the board	Copper particulate contamination	Improve cleaning and handling procedures
Shorts appearing after solder mask	Mask registration or coverage issue	Audit solder mask application process

 

Engaging Your Manufacturer on Failures

When you receive an E-Test failure report, request the following from your supplier:

• Defect location maps showing the physical distribution of failures on the panel
• Root cause analysis for any systematic failure pattern exceeding a 1% defect rate
• Corrective action plans with defined timelines for recurring issues
• Process capability data (Cpk values) for features relevant to the failure mode

 

A supplier that treats E-Test data as a process improvement input — rather than simply a pass/fail gate — is one worth keeping.

E-Test Equipment: Technical Overview

The capabilities of the test equipment your manufacturer operates will shape what is realistically achievable during testing.

Flying Probe Tester Specifications

• Probe heads: four to eight independent units (advanced systems may have sixteen or more)
• Minimum test pitch: 0.1 mm
• Positioning accuracy: plus or minus 10 micrometers
• Integrated camera systems for component location verification
• Four-wire Kelvin measurement for milliohm-level resistance accuracy

 

Test time scales with board complexity. A simple two-layer board may take under a minute; a dense multilayer HDI board can require ten minutes or more per panel.

Fixture Tester Specifications

• Parallel contact: thousands of test points engaged simultaneously
• Cycle time per board: five to thirty seconds
• Minimum pitch for standard fixtures: 0.5 mm
• Contact methods: vacuum actuation or mechanical clamping
• Throughput: 100 or more boards per hour under optimal conditions

 

Fixture costs scale with test point density and board complexity. Typical boards fall in the $1,000 to $5,000 range; high-density designs with thousands of test points can reach $20,000 or more.

Conclusion: Getting the Most from E-Test

Electrical test is not a formality — it is the mechanism that ensures your engineering effort is not undermined by manufacturing defects. A board that passes E-Test is one you can populate with confidence.

For prototypes

Always specify 100% flying probe E-Test. The incremental cost is minimal, and confirming bare board integrity before assembly eliminates a significant source of uncertainty during bring-up.

For production

Collaborate with your manufacturer to identify the volume crossover point where fixture testing becomes more economical. For most board types, this typically falls in the 300 to 500 unit range.

For critical applications

Explicitly state the required IPC-9252 test class in your purchase documentation and request a test report or certificate of conformance. Verification is not something to assume — it needs to be documented.

A board that works the first time is the goal. Rigorous electrical test is how you get there.

Reference Resources

IPC Standards (Available through IPC.org)

• IPC-9252B: Requirements for Electrical Testing of Unpopulated Printed Boards
• IPC-6012: Qualification and Performance Specification for Rigid Printed Boards
• IPC-D-356B: Bare Substrate Electrical Test Data Format

 

Questions to Ask When Evaluating PCB Suppliers

• Which E-Test methods do you offer — flying probe, fixture, or both?
• What is your minimum testable pitch for each method?
• Do you perform 100% electrical test on all boards, or do you use sampling?
• Are you able to test to IPC-9252 Class 3 requirements?
• Do you provide E-Test reports or certificates of conformance with shipments?